In recent years, a chip-stacked semiconductor device having a plurality of semiconductor chips stacked is proposed. In the chip-stacked semiconductor device, through electrodes that penetrate through a silicon substrate are formed on each semiconductor chip stacked. The semiconductor chips are electrically connected to each other via the through electrodes.
FIGS. 25A and 25B are explanatory views showing a conventional chip-stacked semiconductor device, where FIG. 25A is a schematic cross-sectional view of one through electrode out of plural through electrodes provided on each semiconductor chip, and FIG. 25B shows a cross-sectional view along B-B line of FIG. 25A.
As shown in FIG. 25A, a silicon substrate 10 is formed with a ring-shaped isolation trench 11 that penetrates through the silicon substrate 10. Within the isolation trench 11, there are formed a silicon thermal oxide film 12 that covers a side surface of the isolation trench 11, and a polycrystalline silicon film 13 that fills in a portion not filled in by the silicon thermal oxide film 12.
A connection electrode 14 is formed on the silicon substrate 10, and a wiring layer 15 is formed on the connection electrode 14. An opening 17 is formed on the rear surface of the silicon substrate 10 to penetrate through an insulation film 16 formed on the rear surface of the silicon substrate 10 and through the silicon substrate 10. A through electrode 18 is formed within the opening 17. Based on a connection between the through electrode 18 and the connection electrode 14, the through electrode 18 is electrically connected to the wiring layer 15.
The isolation trench 11 is seamlessly formed to surround the through electrode, as shown in FIG. 25B. Accordingly, the silicon substrate 10 at the outside of the isolation trench 11 is electrically insulated from the through electrode 18.
As explained above, to form an electrode on the rear surface of the silicon substrate 10 that is connected to the connection electrode 14 formed on the main surface of the silicon substrate 10, the thermal oxide film 12 and the polycrystalline silicon film 13 buried in the isolation trench 11 for insulating the through electrode 18 from the silicon substrate 10 is necessary around the through electrode 18. However, a forming method of the isolation trench by the conventional technique has the following problems.
To form the thermal oxide film 12 and the polycrystalline silicon film 13, first, the silicon substrate 10 is etched from the main surface thereof so as to form the isolation trench 11. By thermally oxidizing the inner surface of the isolation trench 11, the silicon thermal oxide film 12 that covers the inner surface of the isolation trench 11 is formed. Thereafter, the polycrystalline silicon film 13 is embedded into the gap of the isolation trench 11 not completely filled in by the silicon thermal oxide film 12.
Because the whole isolation trench 11 becomes a dead space, the width of the isolation trench 11 is preferably as small as possible to make it possible isolate the silicon substrate 10 from the through electrode 18.
However, the current silicon etching technique takes a very long time to etch such a narrow (thin) trench, and has a cost problem. Therefore, the isolation trench 11 is formed to have a certain width.
Therefore, as described above, even when the silicon thermal oxide film 12 is attempted to have as large thickness as possible by thermally oxidizing the inner surface of the isolation trench 11, it is difficult to fully fill in the isolation trench 11 with only the silicon thermal oxide film 12. Consequently, as described above, the polycrystalline silicon film 13 is embedded into the gap of the isolation trench 11 not completely filled in by the silicon thermal oxide film 12, by the CVD (Chemical Vapor Deposition) method.
The reason why the polycrystalline silicon film 13 is used as a material embedded into the gap within the isolation trench 11 is described below. When a CVD silicon oxide film is embedded instead of the polycrystalline silicon film 13, a film thickness combined with the thickness of the silicon thermal oxide film 12 becomes so large that strong tension is applied to the silicon substrate 10. Moreover, when a CVD silicon oxide film is embedded instead of the polycrystalline silicon film 13, a total film thickness of the silicon oxide films (the silicon thermal oxide film 12 and the CVD silicon oxide film) formed on the silicon substrate 10 becomes very large. Therefore, it becomes very difficult to flatten the total silicon oxide films. Accordingly, other materials such as a polycrystalline silicon film need to be used, and this complicates the process. Note that, for example, Japanese Patent Application Laid-open No. 2006-261403 discloses a semiconductor device having a through electrode.